Is the AESEBU/Spdif Digital Audio Interface Flawed? - Dunn and Hawksford
http://www.scalatech.co.uk/papers/aes93.pdf
Data på en "typisk" (?) chip
http://www.cirrus.com/en/pubs/proDatasheet/CS8416_F1.pdf
Appendix C
"..An on-chip Phase Locked Loop (PLL) is used to recover the clock from the incoming data stream. Figure 23
is a simplified diagram of the PLL. When the PLL is locked to an bi-phase encoded input stream, it is updated
at each preamble in the bi-phase encoded stream. This occurs at twice the sampling frequency, FS.
There are some applications where low jitter in the recovered clock, presented on the RMCK pin, is important.
For this reason, the PLL has been designed to have good jitter attenuation characteristics, as shown
in Figure 25. In addition, the PLL has been designed to only use the preambles (PDUR=0) of the bi-phase
encoded stream to provide lock update information to the PLL. This results in the PLL being immune to data
dependent jitter affects because the preambles do not vary with the data.
The PLL has the ability to lock onto a wide range of input sample rates with no external component changes.
If the sample rate of the input subsequently changes, for example in a varispeed application, the PLL will
only track up to ±12.5% from the nominal center sample rate. The nominal center sample rate is the sample
rate that the PLL first locks onto upon application of an bi-phase encoded data stream or after enabling the
CS8416 clocks by setting the RUN control bit. If the 12.5% sample rate limit is exceeded, the PLL will return
to its wide lock range mode and re-acquire a new nominal center sample rate..."
-k
