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http://members.chello.nl/~m.heijligers/DAChtml/PLL/PLL1.htm
Det er tydeligvis snakk om en skoleoppgave innen design av DAC med spdif-inngang.
"It is reported that timing errors in the order of 100 ps are perceptible [Watk94]. Some others claim jitter to be audible down to the few picosecond range, also depending upon the spectral content of the jitter.
Now CD players (transports) output their digital data from a buffer, clocked by a crystal oscillator. This data buffer is kept (partially) filled by a feedback-loop controlling the CD spindle speed. Since well-designed crystal oscillators are able to generate highly stable clocks, the digital data could be sent out with a low level of jitter. Any built-in DA converter would use the same crystal-controlled clock, and hence inside the transport good jitter suppression should be feasible.
However when going to external DACs, we have an additional problem. The connection from the CD player to the external DAC is done with a single coaxial wire, carrying a coded serial bitstream according to the S/PDIF standard. In the DAC, this signal is processed by some receiver chip, which has as main task to regenerate a clock signal from the data stream, and use this same clock to latch the incoming bitstream. This is the first point where the `jitter' is created: in the clock generation circuitry of the S/PDIF receiver chip. There is a combination of several factors, which in combination are responsible for the jitter generation at this stage:
The S/PDIF input bitstream arrives at a reasonable high rate of about 2.8 Mbit/sec. Due to the limited bandwith (parasitic capacitance) of the interconnect (plugs and cables), the signal arrives with a degraded slope. This gives uncertainty in the exact determination of the clock edge timepoint. This is also a reason why different cables can sound differently.
The S/PDIF signal is coded to become DC-free. As result it can be (and is) AC-coupled through small isolation transformers and input capacitors. However the lower frequency components can cause variations in the moments where the (limited slope) input signal voltage crosses the reference potential, and thus time shifts in the (amplified) edge. These time shifts would depend upon the actual (sequence of) bit values.
The clock is regenerated in the receiver chip with a PLL circuit. However the on-chip oscillator timing is capacitor-based and not crystal-based. As result it generates significant jitter of its own.
The dynamic characteristics of the receiver PLL are to ensure an error-free clocking of the actual bit values. The dynamic properties of the PLL filter are normally configured with an external resistor and capacitor. These are to be given prescribed values of cheap and small components, causing the PLL to regulate (allow changes in its clock frequency) in the audio range. This seems a bad choice.
The applied external RC PLL filter seems just configured for its dynamic properties, according to standard textbook PLL design. When jitter is of concern however, better low-pass filters can sometimes be used.
The above points 3 to 5 in principal depend upon the actual receiver chip selected. However both the Yamaha YM3623B and the Crystal CS8412 considered by us, are comparable in this respect. Their simple and cheap clock recovery can be motivated by the reasoning that the purpose of the PLL is to clock-in the correct values of the bitstream. To accomplish this, a jitter of half a bit width (170nsec) would be still acceptable. For high-end audio applications they might rightfully expect different circuitry for another more stable clock to drive the DAC chips.
...
When an extra PLL is used to obtain a cleaner clock, it is not immediatly evident how and where this clocksignal should be used, in cooperation with the 'dirty' clock from the receiver: At some point the DAC system should be partitioned by a buffer. The input part of the DAC, including filling the buffer, should then operate on the dirty clock, and the output part of the DAC, starting at reading the buffer, should operate at the clean clock. The buffer size can be chosen between 1 bit of the serial audio stream, 1 sample-word per channel, or a large queue of many sample words."
http://members.chello.nl/~m.heijligers/DAChtml/PLL/PLL1.htm
Det er tydeligvis snakk om en skoleoppgave innen design av DAC med spdif-inngang.
"It is reported that timing errors in the order of 100 ps are perceptible [Watk94]. Some others claim jitter to be audible down to the few picosecond range, also depending upon the spectral content of the jitter.
Now CD players (transports) output their digital data from a buffer, clocked by a crystal oscillator. This data buffer is kept (partially) filled by a feedback-loop controlling the CD spindle speed. Since well-designed crystal oscillators are able to generate highly stable clocks, the digital data could be sent out with a low level of jitter. Any built-in DA converter would use the same crystal-controlled clock, and hence inside the transport good jitter suppression should be feasible.
However when going to external DACs, we have an additional problem. The connection from the CD player to the external DAC is done with a single coaxial wire, carrying a coded serial bitstream according to the S/PDIF standard. In the DAC, this signal is processed by some receiver chip, which has as main task to regenerate a clock signal from the data stream, and use this same clock to latch the incoming bitstream. This is the first point where the `jitter' is created: in the clock generation circuitry of the S/PDIF receiver chip. There is a combination of several factors, which in combination are responsible for the jitter generation at this stage:
The S/PDIF input bitstream arrives at a reasonable high rate of about 2.8 Mbit/sec. Due to the limited bandwith (parasitic capacitance) of the interconnect (plugs and cables), the signal arrives with a degraded slope. This gives uncertainty in the exact determination of the clock edge timepoint. This is also a reason why different cables can sound differently.
The S/PDIF signal is coded to become DC-free. As result it can be (and is) AC-coupled through small isolation transformers and input capacitors. However the lower frequency components can cause variations in the moments where the (limited slope) input signal voltage crosses the reference potential, and thus time shifts in the (amplified) edge. These time shifts would depend upon the actual (sequence of) bit values.
The clock is regenerated in the receiver chip with a PLL circuit. However the on-chip oscillator timing is capacitor-based and not crystal-based. As result it generates significant jitter of its own.
The dynamic characteristics of the receiver PLL are to ensure an error-free clocking of the actual bit values. The dynamic properties of the PLL filter are normally configured with an external resistor and capacitor. These are to be given prescribed values of cheap and small components, causing the PLL to regulate (allow changes in its clock frequency) in the audio range. This seems a bad choice.
The applied external RC PLL filter seems just configured for its dynamic properties, according to standard textbook PLL design. When jitter is of concern however, better low-pass filters can sometimes be used.
The above points 3 to 5 in principal depend upon the actual receiver chip selected. However both the Yamaha YM3623B and the Crystal CS8412 considered by us, are comparable in this respect. Their simple and cheap clock recovery can be motivated by the reasoning that the purpose of the PLL is to clock-in the correct values of the bitstream. To accomplish this, a jitter of half a bit width (170nsec) would be still acceptable. For high-end audio applications they might rightfully expect different circuitry for another more stable clock to drive the DAC chips.
...
When an extra PLL is used to obtain a cleaner clock, it is not immediatly evident how and where this clocksignal should be used, in cooperation with the 'dirty' clock from the receiver: At some point the DAC system should be partitioned by a buffer. The input part of the DAC, including filling the buffer, should then operate on the dirty clock, and the output part of the DAC, starting at reading the buffer, should operate at the clean clock. The buffer size can be chosen between 1 bit of the serial audio stream, 1 sample-word per channel, or a large queue of many sample words."